"We are actively pursuing next-generation technologies at 5nm and beyond to maintain technology leadership and enable our customers to produce a smaller, faster, and more cost efficient generation of semiconductors", said Gary Patton, chief technology officer at GlobalFoundries, the company responsible for manufacturing the IBM chips.
According to the companies' testing, chips produced on a 5nm nanosheet process node can offer a 40 percent performance improvement at the same power envelope or 75 percent power savings with no loss of performance when compared to unnamed 'leading edge 10nm technology available in the market'.
In consumer electronics, 14 nm chips are still stock-standard, but advances from the likes of Intel and Samsung mean that 10 nm versions have started hitting the high-end market.
"This is a major innovation for scaling beyond 7 nanometers", Khare said.
Above: A close-up of IBM's 5-nanometer transistors.
The resulting increase in performance will help accelerate cognitive computing, the Internet of Things (IoT), and other data-intensive applications delivered in the cloud.
Scientists working as part of the IBM-led Research Alliance at the SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering's NanoTech Complex in Albany, N.Y. achieved the breakthrough by using stacks of silicon nanosheets for the transistor, instead of the standard FinFET architecture, which is the blueprint for the semiconductor industry up through 7 nanometers. But, as often happens with technology, this structure is starting to bump up against the limits of how small it can be scaled, and the IBM team says shrinking the fins any further won't do much to improve their performance. This work is the first time that stacked nanosheet devices show advantages in electrical properties over the prevailing FinFET architecture. With this technology, Khare believes that the industry can stay on its path of progress every two or three years.
Above: IBM's 5-nanometer manufacturing equipment. Beyond that, we're properly through the looking-glass but it would still extend Moore's Law beyond its current three-five year remaining lifespan. They're created using Extreme Ultraviolet (EUV) lithography, a process that writes patterns on a silicon wafer using a much higher energy wavelength of light than the current technique. Using EUV lithography, the width of the nanosheets can be adjusted continuously, all within a single manufacturing process or chip design. One of the achievements of the technology is that it can be built using the same manufacturer steps and processes used in 10-nanometer manufacturing. Therefore, while FinFET chips can scale to 5nm, simply reducing the amount of space between fins does not provide increased current flow for additional performance. Certainly not IBM or its chip partners Globalfoundries and Samsung.
At that point, options may include a whole new technique that hasn't been invented yet, or something like Quantum computing, which continues to be a subject of research and development for IBM.